The present invention relates generally to semiconductor transistor design, and, more particularly, to a planar field effect transistor (FET) integrated together with a multiple gate FET on the same substrate where the two types of FETs have top surfaces underneath the corresponding gates that are co-planar with each other, as well as with the top surface of an associated shallow trench isolation region located therebetween.
In the art of semiconductor transistor design it is known to integrate planar FETs with multiple gate FETs (MUGFETs or FINFETs) on the same substrate. However, heretofore it has been unknown to provide a structure and corresponding method for integrating a MUGFET and a planar FET on the same substrate where the top of the MUGFET underneath the gate is co-planar with the top of the planar FET underneath the gate as well as being co-planar with the top of an associated shallow trench isolation (STI) region located therebetween and where the relatively older planar FET technology has added to it the relatively newer MUGFET technology without disruption to the planar technology and with relatively little added cost.